Problems that cause bad silicon

 There are many reasons, but there are few real technical reasons, mainly because the factors that are considered are more likely to cause more missing corners (including many workshops, such as cleaning, inspection, etc.).

Hidden cracks: incoming material, pre-cleaning, inserting, cleaning, pulling, sorting; chipping: C angle, rubber surface, processing, handling; Highlights: impurities; burrs: handling, processing. In the manufacturing process of solar cells, the surface of monocrystalline silicon is produced with sodium hydroxide and isopropanol, and what is the reason? How can we handle it? Generally speaking, the organic matter is not thoroughly cleaned! The second is that the sodium hydroxide is not cleaned!

What are the reasons for the linear slope of silicon wafers? What are the reasons for the linear slope of silicon wafers?

1. The line speed cannot be lower than or exceed the cutting capacity of the mortar. If it is lower than the cutting capacity of the mortar, there will be line marks or even broken lines; on the contrary, if the cutting capacity of the mortar is exceeded, it may cause the mortar flow to fail to keep up, resulting in thick flakes or even line marks, etc.

 2. Mortar flow should be sufficient

 3. Tension of steel wire

What are the possible reasons for the line marks on the silicon wafer? What are the possible reasons for the line marks on the silicon wafer? It depends on the specific occurrence and the direction of the silicon wafer line marks: the main influences are uneven particles of the mortar, jumpers, grooves in the main wheel and debris in the mortar.

 1. The raw material - the silicon block itself has defects such as impurities, which cause the density of the silicon block to be inconsistent or uneven distribution, which is easy to cause line marks;

2. Excipients - The quality of the excipients is not good, such as the wrong material, impurities, etc. In addition, there may be too many repeated use of the excipients;

3. Equipment - the parameters of the equipment should not be the same version, and should be different from machine to machine;

4. Human - the most likely factor, caused by intentional or unintentional or negative work. But at present, line marks are a common phenomenon in most companies. The line mark ratio mainly reflects the level of line cutting and the rate of film formation.

Line marks can be reduced in many ways:

1. Raw materials Start with inspection after prescribing, and control the flow of silicon blocks that may lead to line marks into the wire cutting process.

3. Equipment, perfect maintenance mechanism, unique process formula

4. Personnel consider reducing the line mark rate from a positive aspect. For example, the reward mechanism replaces the punishment mechanism. The main reason is the enthusiasm of the personnel. After all, people play a leading role in production. Complete data and anti-fraud systems, such as the support of major data programs and anti-fraud systems, in the final analysis, the key lies in human process equipment operation data, etc., all need to rely on people to complete dense wiring traces: dense wiring traces are the problem of mortar, and the cutting ability of mortar Low, to solve this problem, you can adjust the cutting speed a little slower, and be more detailed on the slurry problem. Increase the stirring time a bit. This problem can be solved completely. The reason for the pattern of wafer cleaning is that too much IPA has been added, and the time of making silk is too long, so KOH or NAOH needs to be added.

After the silicon wafer is cleaned, the surface is stained, and at a fixed position on the edge of one side, it may... After the silicon wafer is cleaned, there is a stain on the surface, and at a fixed position on the edge of one side, it may be...

There are several possibilities!

1. There is a problem with the previous project, that is, the mud cleaning during wire cutting.

2. Attention should be paid to the cleaning of silicon wafers. Before cleaning, you should be able to see the dirty, insert the dirty side up, extend the ultrasonic time a little, and add lactic acid in the cleaning machine! It should be fine!

Silicon Wafer Process--Challenges

 Cutting line diameter

Thinner dicing lines mean lower kerf losses, which means more wafers can be produced from the same block. However, the cut line is thinner and more prone to breakage.

load

The total area of ​​each cutting is equal to the area of ​​the silicon wafer X the number of silicon blocks cut each time X the number of silicon wafers cut from each silicon block.

cutting speed

The speed at which the cutting table cuts the web through the wire depends largely on the wire movement speed, motor power and wire pull.

Ease of Maintenance

Wire saws require changing the cutting wire and slurry between cuts, and the faster the maintenance, the higher the overall productivity.

Producers must balance these interrelated factors to maximize productivity. Higher cutting speeds and higher loads will increase the pulling force of the cutting wire, increasing the risk of wire breakage. Since all the silicon wafers on the same silicon block are cut at the same time, as long as one cutting line breaks, all the partially cut silicon wafers have to be discarded. However, it is also not advisable to use thicker and stronger dicing lines, which reduces the number of wafers produced per dicing and increases the consumption of silicon raw materials.

Wafer thickness is also a factor that affects productivity, as it relates to the number of wafers produced per block. Ultra-thin silicon wafers present additional challenges for wire saw technology, as its production process is much more difficult. In addition to the mechanical brittleness of the silicon wafer, if the wire sawing process is not precisely controlled, fine cracks and bends can negatively impact product yield. Ultra-thin wafer wire saw systems must provide precise control over process linearity, cutting line speed and pressure, and cutting coolant.

Regardless of the thickness of the silicon wafer, crystalline silicon photovoltaic cell manufacturers have put forward extremely high requirements on the quality of the silicon wafer. Silicon wafers must be free of surface damage (fine cracks, wire saw marks), topographical defects (bending, bumps, uneven thickness) should be minimized, and the requirements for additional back-end processing such as polishing should be minimized.

Wafer grade classification and standard

 1）.First-class products (Class I tablets)

1. Physical and chemical properties ①Model: P crystal orientation <100>±1°; 18 3 ②Oxygen content: ≤1.0×10 at/cm; 16 3 ③Carbon content: ≤5×10 at/cm; ④Minority carrier lifetime :τ=1.3-3.0μs (data of bare chip under test voltage ≥20mv); ⑤Resistivity: 0.9-1.2, 1.2-3.0, 3.0-6.0Ω·cm; 2 ⑥Dislocation density: ≤3000 pieces/cm ; 2. Geometric dimensions ①Side length: 125×125±0.5mm; ②Diagonal: 150×150±0.5mm; ③Concentricity: the difference between the chord lengths of any two arcs ≤1mm; ④Perpendicularity: the clamp on any two sides Angle 90°±0.3°; ⑤Thickness: 200±20μm; (thickness at center point≥195μm, thickness at four points at the edge≥180μm) 180±20μm; (thickness at center point≥175μm, thickness at four points at edge≥160μm) ⑥TTV: ≤30μm; ⑦Curvity: ≤40μm; 3. Surface indicators ①Line marks: no visual marks; ②Visual surface: no contamination, no water stains, dyeing, white spots, fingerprints, etc.; ③No chipping, no Visual cracks, smooth edges, no warping visually;

2）. Qualified products (Class II tablets)

1. Physical and chemical properties ①Model: P crystal orientation<100>±1°; ②Oxygen content: ≤1.0×1018at/cm3; ③Carbon content: ≤5×1016at/cm3; ④Minority carrier lifetime: τ=1.0-1.2μs (Data of bare chip under test voltage ≥20mv); ⑤Resistivity: 0.5-0.8Ω·cm; ⑥Dislocation density: ≤3000 pieces/cm2; 2. Geometric dimension ①Side length: 125×125±0.5mm; ②Diagonal: 150×150±0.5mm; ③Concentricity: The difference between the chord lengths of any two arcs ≤1.5mm; ④Perpendicularity: The angle between any two sides is 90°±0.3°; ⑤Thickness: 200±20μm;( Thickness at center point≥195μm, thickness at four edge points≥180μm) 180±20μm; (thickness at center point≥175μm, thickness at four edge points≥160μm)

⑥TTV: ≤30μm; ⑦Bending degree: ≤40μm; 3. Surface indicators ①Line marks: no obvious line marks, no bumps when touched. ② Range of edge collapse: edge collapse is not "V" shape, length × depth ≤ 1 × 0.5mm, number ≤ 1 piece/piece; no visible cracks, smooth edges, no warping visually;

3）.Other products (Class III tablets)

1. Physical and chemical properties ①Model: PN crystal orientation <100>±3°; ②Oxygen content: ≤1.0×1018at/cm3; 16 3 ③Carbon content: ≤5×10 at/cm; ④Minority carrier lifetime: τ＜ 1.0μs (data of bare chip under test voltage ≥20m); ⑤Resistivity: ≤0.5Ω·cm; ⑥Dislocation density: >3000 pieces/cm2; 2. Geometry ①Side length: 125×125±1.0mm ; ②Diagonal: 150×150±1.0mm; ③Concentricity: the difference between the chord lengths of any two arcs ≤1.5mm; ④Perpendicularity: the angle between any two sides is 90°±0.5°; ⑤Thickness: <160μm 3. Surface indicators ① There are obvious line marks, and the touch has a bumpy feeling.

Note: As long as it meets any one of the third "extraordinary products (Class III tablets)", it will be judged as a non-conforming product.