Silicon Wafer Process--Challenges

 Cutting line diameter

Thinner dicing lines mean lower kerf losses, which means more wafers can be produced from the same block. However, the cut line is thinner and more prone to breakage.

load

The total area of ​​each cutting is equal to the area of ​​the silicon wafer X the number of silicon blocks cut each time X the number of silicon wafers cut from each silicon block.

cutting speed

The speed at which the cutting table cuts the web through the wire depends largely on the wire movement speed, motor power and wire pull.

Ease of Maintenance

Wire saws require changing the cutting wire and slurry between cuts, and the faster the maintenance, the higher the overall productivity.

Producers must balance these interrelated factors to maximize productivity. Higher cutting speeds and higher loads will increase the pulling force of the cutting wire, increasing the risk of wire breakage. Since all the silicon wafers on the same silicon block are cut at the same time, as long as one cutting line breaks, all the partially cut silicon wafers have to be discarded. However, it is also not advisable to use thicker and stronger dicing lines, which reduces the number of wafers produced per dicing and increases the consumption of silicon raw materials.

Wafer thickness is also a factor that affects productivity, as it relates to the number of wafers produced per block. Ultra-thin silicon wafers present additional challenges for wire saw technology, as its production process is much more difficult. In addition to the mechanical brittleness of the silicon wafer, if the wire sawing process is not precisely controlled, fine cracks and bends can negatively impact product yield. Ultra-thin wafer wire saw systems must provide precise control over process linearity, cutting line speed and pressure, and cutting coolant.

Regardless of the thickness of the silicon wafer, crystalline silicon photovoltaic cell manufacturers have put forward extremely high requirements on the quality of the silicon wafer. Silicon wafers must be free of surface damage (fine cracks, wire saw marks), topographical defects (bending, bumps, uneven thickness) should be minimized, and the requirements for additional back-end processing such as polishing should be minimized.